For accelerating designing various memories, a memory compiler has been widely used in the industry. By means of the memory compiler, the researchers can design various memories with different sizes and storage capacities according to different requirements and features. Since the designed memories can be quickly applied to the production line, the time period required to fabricate the memories will be shortened.
FIG. 1 schematically illustrates the architecture of a memory generated by a conventional memory compiler. As shown in FIG. 1, the memory 50 comprises a logic controller 20, a word line driver (WL driver) 10, plural memory cores 11˜1m, plural selectors 21˜2m, and plural output drivers 31˜3m. 
Generally, during the writing/reading process of the memory 50, the logic controller 20 may control all internal circuits of the memory 50. Moreover, the WL driver 10 can decode a specified word line according to a corresponding address data and activate the specified word line. The plural memory cores 11˜1m comprises plural word lines and plural bit lines (not shown). The word lines are connected with the WL driver 10. The storage capacity of the memory 50 is defined by the plural memory cores 11˜1m collaboratively.
Take the first word line WL1 as an example. The first word line WL1 is connected with the WL driver 10 and all of the memory cores 11˜1m. When the first word line WL1 is activated, the memory cells of the memory cores 11˜1m connected with the first word line WL1 are all activated. In other words, the higher storage capacity of the memory 50 indicates that the number of the memory cores 11˜1m is larger and the word line is longer.
Moreover, the plural selectors 21˜2m comprise respective multiplexers (not shown) and respective sense amplifiers (not shown) for selecting the corresponding bit lines and sensing the data of the corresponding bit lines. Moreover, the data of the corresponding bit lines are outputted from the output drivers 31˜3m. 
Generally, after the specified design parameters are inputted into the memory compiler, the memory 50 can be generated by the memory compiler according to the practical requirements.
For example, after a specified storage capacity is inputted into the memory compiler, the number of the memory cores 11˜1m, the number of the selectors 21˜2m and the number of the output drivers 31˜3m are calculated by the memory compiler. The memory cores 11˜1m, the selectors 21˜2m, the output drivers 31˜3m, the logic controller 20 and the WL driver 10 are combined as the memory 50. Generally, one memory core corresponds to one selector and one output driver. That is, the m memory cores 11˜1m correspond to the m selectors 21˜2m and the m output drivers 31˜3m. After the above circuits are placed by the memory compiler, the memory 50 is produced.
With increasing development of the semiconductor manufacturing process, memories can be fabricated by the advanced manufacturing process. However, if the memory 50 is fabricated by the advanced manufacturing process under the 40 nm process, the yield rate of the memory 50 is impaired. It was found that the process variation may cause reduction of the induced current of the memory. Since the induced current is insufficient to allow normal operations of the memory, the yield rate of the memory is impaired. The memory cell that cannot be normally operated because of the process variation is usually referred as a weak memory cell.
Conventionally, a method of increasing a word line voltage is provided for allowing the normal operations of the weak memory cell. After the word line voltage is increased, the weak memory cell can be normally operated, and the yield rate of the memory can be effectively enhanced.
FIG. 2 is a schematic circuit diagram illustrating a conventional word line boost circuit. The word line boost circuit 308 is used for increasing the word line voltage.
As shown in FIG. 2, the word line boost circuit 308 comprises a regulator 306, plural switch transistors SW1, SW2, SW3, a boost capacitor C1, and a switch timing circuit 302. The switch timing circuit 302 receives a bank select signal. According to the bank select signal, the switch timing circuit 302 controls the switch transistors SW1, SW2 and SW3. When the word line is activated, the superposed voltage of a power supply voltage VDD and an adjustable voltage VDELTA is transmitted from the boost capacitor C1 to a word line driver (WL driver) 304 and then sent to the memory array.
The adjustable voltage VDELTA is determined by the regulator 306 according to a reference voltage VREF from a programmable voltage source 310. In other words, the magnitude of the voltage increased by the word line boost circuit 308 may be determined according to the reference voltage VREF from the programmable voltage source 310.
However, the regulator 306 of the word line boost circuit 308 and the programmable voltage source 310 consume a great amount of electric power and occupy very large layout areas.
Moreover, when the word line boost circuit 308 is applied to the memory compiler, some problems may occur. For example, if the number of the memory cores of the memory is different, the length of the word line is different. That is, if the storage capacity of the memory is changed, it is necessary to adjust the magnitude of the reference voltage VREF of the word line boost circuit 308. In other words, the conventional word line boost circuit is not user-friendly.